The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
In analog circuit designs, circuit performance is largely dependent upon device matching (e.g., matching of respective sizes of a plurality of similar devices in a circuit). For example, in fin field effect transistor (finFET) circuits, mismatches in device width (W) and length (L) of finFET devices may degrade performance of the circuit. Due to process limitations in manufacturing of the devices (e.g., photolithography, etch, and chemical mechanical planarization process limitations), satisfying various design requirements (e.g., width, length, spacing, and density requirements) while minimizing mismatching is increasingly difficult. For example, as device size decreases (e.g., to increase density), device mismatch increases.